1. Field of the Invention
The present invention generally reates to an engineering change facility for a semiconductor device module or substrate on which multiple chips are mounted and, more particularly, to such a facility having delete lines on both major surfaces of the module.
2. Description of the Prior Art
Prior art packages for semiconductor devices have provided for making engineering changes or repairs subsequent to module manufacture. Generally, alternative circuit pathways are made available through the module or substrate on which multiple chips are mounted. If one of the circuit pathways is to be replaced because of design change or component failure, the undesired pathway is isolated electrically by deleting specially provided connecting line portions (delete lines) located on a major surface of the chip supporting module or substrate. The isolated, undesired circuit pathway then may be replaced by an added engineering change (EC) wire.
One example of an EC facility in which delete lines are provided on a major surface of a printed circuit board is described in U.S. Pat. No. 3,923,359, issued Dec. 2, 1975 to W. Newsom. Another is shown in U.S. Pat. No. 4,254,445, issued Mar. 3, 1981 to C. W. Ho and assigned to the present assignee. The latter deals with a semiconductor chip package.
In an article in the IBM.RTM. Technical Disclosure Bulletin, August 1978, pg. 957, R. Weiss discloses another EC printed circuit board arrangement using delete lines on the upper board surface and substitute connecting wires over the bottom board surface which are added to the bottom of insulated pins extending through the board.
In each of the above cases, which are exemplary of the prior art, all EC delete lines are located on only one major surface of the board, module or substrate. Thus, all of the space required by the delete lines must be accommodated on the said one surface. Additionally, through-connections running between both major surfaces of the board, module or substrate cannot be fully electrically isolated from circuits connected thereto and bypassed simply by use of such delete lines.